Most often, computer programs are initially written in high-level program statements. In order to be executed by a computer, the program statements are compiled into machine instructions that a microprocessor can recognize and execute. The machine instructions are selected from a set of machine instructions unique to a particular Instruction Set Architecture (ISA).
In the field of ISAs, there have arisen two fundamentally different types of instruction sets: the Complex Instruction Set Computer architecture (CISC) and the Reduced Instruction Set Computer architecture (RISC). The CISC architecture utilizes an instruction set that allows for complicated and flexible ways of calculating such elements as memory addresses. One of the defining characteristics of the CISC architecture is the use of variable length instructions, which adds additional complexity to the decoding hardware. Although very powerfully, all the complexity of the CISC instruction set usually requires additional clock cycles to execute each machine instruction.
A RISC processor, on the other hand, is designed to operate more efficiently by processing a relatively smaller set of instructions. The RISC design is based on the premise that most of the instructions a computer decodes and executes are simple. As a result, RISC architecture limits the number of instructions that are built into the microprocessor, and optimizes each so it can be carried out very rapidly, usually within a single clock cycle.
It is possible for computer program statements that have been compiled into machine instructions for a CISC processor to be translated in order to be executed on a RISC processor. This translation process is normally carried out by a binary translator, which typically consist of a set of instructions stored in memory.
The RISC machine executes the translated instructions by using the RISC instruction set to emulate how the untranslated instructions would be executed on a CISC processor. Practitioners in the art will understand, that when a RISC processor emulates a CISC program, many of the inherent performance advantages of the RISC processor are missed.
Consider, for example, the conditional instruction. A conditional instruction performs an operation, such as transferring the flow of execution from one instruction to another, when a specified condition is true. If the condition is false, the conditional instruction is treated as a no-operation (i.e., an instruction having no effect on the machine's current architectural state).
A conditional instruction is typically based on the results of a previously executed arithmetic instruction, such as the compare instruction. A compare instruction, when executed on a CISC processor, compares two values by subtracting one value from a second value and updates a set of status flags based on the difference of the two values. The actual difference generated by the comparison, however, is not saved in a memory location (i.e., is architecturally transparent).
The status flags are typically represented by one-bit fields in a dedicated register. In one prior art CISC ISA, the status flags include a Zero Flag (ZF) indicating the difference is 0, a Sign Flag (SF) representing the most significant bit of the difference, and an Overflow Flag (OF) indicating the difference is too large or too small to be represented in the number of bits allocated to store the result.
The conditional instruction, when executed on a CISC processor, evaluates a logical combination of the status flags in order to determine whether the condition of the conditional instruction is met. In one example, the conditional instruction evaluates the complex expression (ZF=1 or SF|=OF).
The RISC microprocessor, however, typically has no native support for setting status flags (i.e., dedicated registers). Therefore, a RISC processor emulates a CISC processor executing a compare instruction by allocating bit fields within a general purpose register for the setting of status flags.
To emulate a conditional instruction evaluating the set of status flags, the RISC processor employs a series of instructions provided in the RISC instruction set. Use of the series of RISC instructions, however, misses the performance advantage of the RISC processors. Typically, the instruction set of a RISC processor includes one conditional instruction that efficiently evaluates a single value generated by a previously executed compare instruction.
Therefore, it can be appreciated that there is a need for a method of translating conditional instructions that are originally dependent on a logical combination of status flags, to be dependent on an actual difference generated by a previously executed compare instruction.